Another idea: have raffles. For example everyone who donates $10 or more is entered into a draw, and draws take place at donation milestones (for example every $50,000 donated). Prizes can be ORSoC development boards, for example, to provide something relevant to donators, or other related products, or a Mouser or Digi-Key gift card, that kind of thing.

I'm sure this kind of thing will draw some people and convince others to pay the minimum amount to be entered into the draw when they wouldn't have otherwise.

That would make for nice banners, too: "Donate to the OpenRISC ASIC, win an OpenRISC Development Kit"... and so advertise the project.

Another thought, one that's related to the other post on this forum and what some others said here: you must have a roadmap of money goals, hopefully starting low.

The problem is just looking at the donation page people can get discouraged. Creating an ASIC costs a lot of money, and certainly people who don't have a real idea of the costs (which would be most people, I'd say) would put it at a million dollars plus, or whatever high goal. Looking at the donation level people would just think "what's the point of donating, they'll never get enough money to create the ASIC."

If there were some realistic goals, this would for one thing show that this is a serious project. By this I mean that it would prove that the people behind the project have a good idea how to get it done, what costs are involved and where to turn to in order to manufacture and test the ASIC. That by itself would raise confidence levels.

Then there's the point of setting a low goal. It may be enough that the low goal is "do a small test run". If that goal is low enough then people may be willing to donate to reach it. Then it's off to the next goal, etc. I would suggest that when a goal is reached there will be a survey of whether to take that step or wait (assuming that a bit more money can reach a similar but better goal, for example a chip on a better process).

Our initial goal is to release as much as possible as "open source", but if this will become a deal-breaker for the selected ASIC manufacture, then we might have to accept this limitation. We think that it's more important that we act as one group, that synchronize our purchases (act as one purchase entity), getting larger accumulated volumes from the whole community.



We were initially aiming at getting 20-30 samples and also purchase risk-parts after some initial testing, so that we could provide all donors with a dev-board with the OpenRISC-ASIC mounted. But with a smaller fund we might have to settle with getting 10-20 samples. It would be great to hear more suggestions/ideas on how we can try and get as many samples out of a test-run and the lowest cost :-) !!!

Good ideas, will try and implement these. We see allot of good feedback also from other posts, keep them coming.....

Has anyone any experience from getting funding from EU? Have heard that the process takes a long time and requires allot of paper work. Is it worth doing it?



I think that it would be more cost efficient to add a FPGA-die into the same package (SiP or MCM).But it's really a cool idea that we also have being thinking about :-)
It would be interesting to know if someone have experience of integrating programmable-logic into a custom ASIC design?



We only moderate the first post posted by a user, then all posts from that user are being sent without moderation. But since we have so many users, the servers work hard sending allot of emails, occasionally creating an email queue causing delays.

I'd rather have SDRAM die there, 32 MBytes would be enough for 90% of chip application.

They will offer a better deal than MOSIS. If a European university research group used this, a sample test run could be had for free. Licensing would need to be negotiated but this is the best possible way to make the most of the donations probably.



Somebody would need to do the logic design, layout and simulation first...last I checked the OpenCores FPGA core was in the "planning" stage whereas Ethernet, SPI, I2C, etc are all working rather well (i.e. it can be fabbed now). Additionally, a verilog/netlist compiler which targets this FPGA would be needed. It may be possible to use ABC from Dr. Mishchenko's research group at Berkeley for a front end (http://www.eecs.berkeley.edu/~alanmi/abc/), then a back end mapping for the custom FPGA fabric will be needed.

After a custom chip is implemented, fully tested, and characterized a full fab run will cost $500k ~ $1m. If donations are used for a full run, then the donation target should be much higher than where it is now. Have you asked RMS if he might make an announcement or two about open hardware? I cannot think of a better way to get the word out than to use the marketing machine behind the FSF and the news sites that follow them.

There is an article about Open Hardware License at LinuxDevices.com.
http://www.linuxfordevices.com/c/a/News/Open-Hardware-License-OHL-11/
http://www.ohwr.org/
It would be nice to see similar article about OpenRISC ASIC initiative there.

Some people are wondering what can be done with the money available or when there will be enough money to ask that question, but I don't think this approach of "wait and see" is good for the request for funding, because nothing gets done until it gets to the point where one's sure there won't be much more funding, which can be quite counterproductive. Having remotely clear goals or possible paths ("we will try to aim at A, and if that's not possible we'll go B or C") makes the project more attractive. I think people should start talking about numbers to answer these questions so donors have an idea of what will be done instead of simply hoping something good will eventually come out of it. There's already some of that in that other thread called "Roadmap", but I don't think providing such rough figures is enough.

Given current total (17k-18k$), it is clear an ASIC design in a moderately new technology is not realistic. Leaving aside the tools for now (both software and hardware; design and measurements), prototyping is very expensive. There's "cheap" access to small ASIC runs via entities like MOSIS or Europractice but a small prototype in a 0.35um process is already in the order of magnitude of that amount of money. Going even farther, TSMC's or UMC's 130nm processes in MPW are in the order of several k$ per square millimeter. And 90nm virtually doubles. The problem of characterization is more complex. Subcontracting also the packaging is not particularly cheap either (although it depends a lot on the number of pins in mind), but then you have to prepare PCBs for measurements, interfacing debugging elements, possibly external hardware to test connectivity, etc. By the time you go to the foundry you may already have tested loads of functionality on simulations or FPGAs, but there are many practical problems (clock distribution, temperature, power regulation) that won't show up until you actually make the ASIC. It is very likely you'll have to do it all over again at least once more, specially if the designers are new to the technology/standard cell libraries. Without knowing anything about functionality or performance it's still impossible to come up with a budget, but without -tentative- technical roadmaps it is also very unlikely to get much more attention (money or publicity) than there is already. Even if you could double or triple the figures, I don't see an attractive ASIC happening. Add design tools, standard cell libraries (which can be cheap for non-commercial purposes, but in the end you want to sell them so you have to knock at the doors of the foundries), etc, and it's extremely expensive.

I don't have direct experience on gate arrays, but I suspect the problem is similar. Testing and the more than probable design iterations are gonna be too expensive.

Some of these drawbacks might be reduced with collaboration from public entities, specially universities. This looks like an amazing opportunity for grad/undergrad projects, and they could put time and resources. It would have the potential to reduce a lot of pressure from the need of testing equipment, alleviating costs.

On the other hand, there may not be enough resources for an ASIC prototype with donations alone, and you'll definitely NOT get any respectable amount of buyers without anything done but, if FPGA prototyping is the first step.. why not go FPGA all along? Invest the money on a good FPGA platform, the best affordable with whatever the budget is, and develop everything there. Useful and verifiable IPs will come out of it even if the project doesn't go any further, so that's useful per se; consider it a big opencores project but with an actual budget.

What about the ASICs? Well, even though Xilinx discontinued their "Hardwire" option, Altera still have their "Hardcopy" services. Once you have a fully functional design in your FPGA you can pay them to build the ASIC version of it. At that point you have a relatively complex design working inside an FPGA. It's already documented and tested, and you have an estimation of the time to market: you can finally offer it as a usable product, and attract buyers. If you get enough buyers, you beat the NRE costs and go for it, and if you don't you haven't wasted any money (unlike with the ASIC, since the only way of making it profitable is achieving production status). Xilinx now has no "hardwire" but offers something called "Easypath" instead, a sort of simplified FPGA version. It's closer to an FPGA (it's actually still an FPGA), but it's cheaper than regular FPGAs in high volumes (NRE still high though) because they cut a lot of the testing costs, and you can have your verified "specific FPGAs" in a few weeks. Altera's solution looks more attractive to me in that you have a more usable version of your FPGA prototype (as FPGAs are flexible but a bit messy to use) and it's still something you know will work once built, but it's just an idea.

Anyway, I think there should already be some action if one wants more funding or participation. Study the alternatives. Start checking figures, possible routes, loads of "what if..". If you're using FPGAs at any point (which I'm guessing will happen either way), talk to manufacturers. They may like the publicity, and even if they make a small contribution it will likely have a huge impact on the progress of the project. Maybe you get some free development boards. Who knows, you may even get away with some special price or agreement for these mass-production options.

So, my two cents on this: No matter what the technologies on the table are, they should be explored early if one wants to attract attention. I would seek collaboration from other organisms as early as possible to see how costs can be reduced, and do budget estimations for different possibilities and not just an estimation of the order of magnitude, setting more specific goals, and making sure in each case that by the time the budget is spent, there is as much to show to the public as possible. Otherwise, half-built prototypes won't bring any more money once it's over.

One more thing.. it's way too early to think about unitary prices, as there's a huge interval depending on the technology and volume that should be studied. We could be talking about $3 or $300 without having any idea.

The "full FPGA" approach can be very (very) expensive (per unit) for high-end designs, and in the context of a RISC processor with peripherals I doubt it makes any sense (these high volume options FPGA manufacturers offer don't lead to cheap units, exactly), but if the target is a proof of concept to bring funding for a full-custom ASIC in a project expansion, or for research/education purposes in a low volume market, it's an excellent first step.

The ASIC (be it full-custom, gate arrays or whatever), which would bring low unitary costs, is the most attractive final result, something equally accessible to universities, industry and hobbyists, but if there isn't enough funding to guarantee a first working prototype it is the least likely to reach a useful goal.

It is not; research must be original and there are existing implementations of the same thing (e.g. LEON3/GRLIB).

How about being more agile in advertising the whole project?
There's being a lot of talking about open hardware movement lately,
but I can't remember OpenCores being mentioned somewhere. Why not use the momentum.
There are a couple of high volume open source magazines like Linux Journal and Linux Magazines which I'm sure would like the story.
Than there are hardware oriented magazines (embedded stuff) like Circuit Cellar or Elektor.
A nice presentation with a kind of FPGA example would make great an article and possibly attract more people to the project.

First, 10% donations. I donate 7 euros now and commit to 70 euros when the project achieve some goal. There is no guarantee that people will donate the rest but at least we will have some guidance for the financial potential of the project.
Secondly, donations are for microprocessor and not for the web page. They should stay in a bank as we achieve the goal, even if it takes years.
I apologize for my English! You can edit my post.

EETimes, 11 years ago, OpenRISC article
http://www.eetimes.com/electronics-news/4151330/Free-32-bit-processor-core-hits-the-Net

As person from "outside world" I mostly agree with the comments above. I have the following idea to help raising money: if you could sell FPGA or flash (e.g. Xilinx) chips preloaded with the OR core + at very least some basic hardware (SRAM - not SDRAM, SPIs, UARTs, serial Flash for program memory and possibly Wishbone interface as a serial bus) in DIY-friendly package (no BGA, please). I'd definitely buy the pre-configured chips instead of e.g. AVR to use in my projects. If there's such project, from which the $ goes to OR, please post a link on the fund raising page.